Timing related failures occur in integrated circuits (ICs) for various reasons that include variations in the manufacturing process, physical defects, thermal and environmental variations. Once an IC device shows a failure, it is desirable to determine if the failure is indeed timing related and then try to confine the timing range for that failure.
In general, a semiconductor test system provides test signals to an IC device under test (DUT), and receives output signals from the DUT generated in response to the test signals. The response outputs are sampled by strobes with specific timings to be compared with expected value data to determine whether the DUT performs correctly or not.
FIG. 1 is a schematic block diagram showing an example of conventional semiconductor test system, which is a cyclized (cycle based) test system. In the test system of FIG. 1, a pattern generator 2 receives test data from a test processor 1. The pattern generator 2 generates pattern data which is provided to a wave formatter 4 and an expected value pattern which is provided to a pattern comparator 7. A timing generator 3 provides timing data and waveform data to the wave formatter 4. The timing generator 3 also generates timing signals to synchronize the operation of the overall system.
The pattern (test vector) data defines “0” and “1”, i.e., logic level of the test signal waveform. The timing data (time-sets data) defines timings (delay times) of the rising and falling edges of the waveform relative to the starting edge of the test cycle to which the waveform belongs. The waveform data specifies a waveform in a particular test cycle such as an RZ (return to zero), NRZ (non-return to zero) or EOR (exclusive OR) waveform. Based on the pattern data from the pattern generator 2, the test cycle pulses (time-sets), the timing data and waveform data from the timing generator 3, the wave formatter 4 forms a test signal having specified waveforms and timings. The wave formatter 4 sends the test signal (test pattern) to the DUT 9 through a driver 5.
A response signal from the DUT 9 is compared with a reference voltage at a predetermined strobe timing by the analog comparator 6. The resultant logic signal is provided to the pattern comparator 7 wherein a logic comparison is performed between the resultant logic pattern from the analog comparator 6 and the expected value pattern from the pattern generator 2. The pattern generator 7 checks whether two patterns match with each other, thereby determining pass or failure of the DUT 9. When a failure is detected, such failure information is provided to a failure memory 8 and is stored along with the information of the failure address of the DUT 9 from the pattern generator 2 in order to perform the failure analysis.
As noted above, in the conventional semiconductor test system such as shown in FIG. 1, a test signal to be applied to the DUT is produced in a cycle by cycle manner based on three kinds of data, i.e., pattern (vector) data, timing data and waveform data. This data structure in the conventional technology will be further described later with reference to FIG. 3 to illustrate the difference from the event based test system which implements the present invention. In the cycle based test system, because the timing of the test signal is created by selecting one or more time-sets for the corresponding test cycle, the ability and flexibility for timing analysis of an IC device under test is limited.
Namely, in debugging the timing failure of the IC device, it is desirable to freely change a selected portion of the timing of the test signal. In the semiconductor test system at the present time, however, such changes of a portion of signal is obtained by changing the timings of the signal waveform. This is done by replacing the time-sets in that particular portion of the test signal in the particular test cycle by adding or removing the time-sets to redefine the test waveform. The main difficulty is that the cycle based semiconductor test system has only a limited number of time-sets.
For example, the T6600 series IC tester of Advantest Corporation, Tokyo, Japan, has six time-sets, and some other commercially available IC testers have up to eight time-sets. While these time-sets are sufficient to define nominal signals in the present day IC devices, often, extra time-sets are not available to redefine a test signal to stretch the timing (i.e., to shift or offset the timing of a particular edge to attain an extended timing). In the case of a large circuit, multiple signals and multiple portions within each signal may require such stretching. Due to a limited number of time-sets, it is very difficult to perform timing related failure debugging in the semiconductor test system in the conventional technology.
Therefore, there is a need for developing a systematic method that can identify what portion of a signal needs to be stretched or shrunk and freely execute such timing changes. Also, such a method should not use the conventional time-sets to define waveforms because only a limited number of time-sets are available.